1. Field of the Invention
The present invention relates to a video display controller for use in terminal equipment for a computer, television game apparatus or the like.
2. Prior Art
Recently, various kinds of display control systems which display animation and still images on a screen of a CRT (cathode-ray tube) display unit under the control of a CPU (central processing unit) have been developed. FIG. 1 shows one example of such conventional systems which comprises a video display controller (hereinafter referred to as "VDP") 1 and a central processing unit (CPU) 2. The system further comprises a memory 3 which includes a ROM (read only memory) for storing a variety of programs to be executed by the CPU 2 and a RAM (random access memory) for storing other necessary data. The CPU 2 outputs data representative of still and animation images to be displayed on a screen of a CRT display unit 4 to the VDP 1 which in turn stores the still and animation data into a video RAM (hereinafter referred to as "VRAM") 5.
The VDP 1 comprises two interface circuits 6 and 7, an image date processing circuit 8, a horizontal counter (H counter) 9, a vertical counter (V counter) 10, and two decoders 11 and 12. The H counter 9 is a binary counter having a count range of "0" to "340" for counting a clock pulse .phi. having a cycle of 186.2 nsec. Each time the clock pulse .phi. is counted 341 times, the H counter 9 outputs a pulse signal CP to the V counter 10. The time period, during which the H counter 9 counts the clock pulse .phi. 341 times, coincides with the sum of a horizontal scanning period and a horizontal blanking period of the screen of the CRT display unit 4. The V counter 10 is a binary counter having a count range of "0" to "261" for counting the pulse signal CP. The time period, during which the V counter 10 counts the pulse signal CP 262 times, coincides with the sum of a vertical scanning period and a vertical blanking period of the CRT display unit 4. The image date processing circuit 8 reads out the image data previously stored in the VRAM 5 in response to a display command supplied from the CPU 2, and displays a color video image on the screen of the CRT display unit 4 in accordance with the read image data. More specifically, the image date processing circuit 8 produces a horizontal synchronization signal and a vertical synchronization signal in accordance with outputs of the decoders 11 and 12 and then combines these synchronization signals to form a composite synchronization signal CSYNC to be supplied to the CRT display unit 4. Also, the image data processing circuit 8 determines the color of display element (dot) at each dot display position on the display screen in accordance with the image date read from the VRAM 5, and sequentially outputs color signals R, G and B (red, green and blue) in accordance with the scanning position on the screen designated by the outputs of the decoders 11 and 12. The color signals R, G and B outputted from the image data processing circuit 8 are supplied to the CRT display unit 4 to thereby display color dots on the screen of the CRT display unit 4.
Such a conventional video display controller described above is so constructed that color signals R, G and B for displaying the leftmost display element on each horizontal scanning line of the screen are outputted a predetermined time period after the corresponding horizontal synchronization signal is issued. However, due to the difference in characteristic of the CRT display unit 4, the display element designated by the color signals R, G and B outputted at the above time instant is not always displayed at the leftmost position of the screen, and it is unavoidable that the display element is displayed at a position on the screen which is deviated a distance corresponding to several display elements rightwardly or leftwardly from the correct display position. In this case, the whole video image is displayed in an area of the screen which is shifted to the left or to the right from the correct display area of the screen, so that the leftmost portion or the rightmost portion of the video image may be hidden. The same kind of problem as above may also occur with regard to the display operation in the vertical direction of the screen. Thus, with the conventional video display controller, the overall display image on the screen cannot have been horizontally or vertically moved to correct its display position and to recover the hidden portion of the image.